1. Field of the Invention
The present invention relates to a semiconductor test system and, more particularly, to a semiconductor test system for inspecting a memory IC chip and with self-inspection of a memory repair analysis module.
2. Description of Related Art
Accompanied by continuous development of techniques, various kinds of memories and memory capacity have been developed, such as DRAM, SRAM, flash memory, DDR DRAM (Double Data Rate DRAM), and SOC. The memory capacity is increased in a multiple manner. The conventional DRAM with 4 Mb or 16 Mb has been extended to DDR or RAM with GB.
As such, when the capacity of the memory is getting bigger and bigger, the probability of generating a failure memory cell (or called memory bit) during fabrication of the semiconductor is inevitably getting higher and higher and the rate of the production yield is reduced due to increase of the quantity of the damaged memories. Therefore, the test of the memory plays an important role, in which the test bench (machine) or equipment dominates an absolutely important part. If the test bench or equipment is in failure or out of order, big loss in cost will be incurred. In addition, in many occasions of incurring failure or an abnormal condition, the bench or equipment itself will not inform or notify the situation automatically and it is hard to trace back when the failure or abnormal condition starts, which quite often results in a serious event of withdrawing. Not only loss of cost is incurred, but also reputation of the company will be affected.
However, since the memory provides a memory zone with columns and rows required normally and at the meantime is reserved with a redundancy circuit (or called “redundancy cell”), the technique of laser fuse is mainly used to alter the circuit path so as to replace a damaged memory cell in a normal zone, thereby achieving the objective of raising yield. Thus, an important step before proceeding with the laser fuse is using the technique of memory repair analysis (MRA). That is, a memory bit position with failure after the test is calculated, analyzed and judged if it may be repaired. If repair can be made, it has to decide how to replace useful information for repairing so as to proceed with the subsequent repairing procedures. Thus, a memory repair analysis device occupies a rather important and indispensable part in the whole memory test process.
Although each of the global enterprises in semiconductor test equipments possesses its own techniques of self-inspection for the test bench, the techniques are directed to inspecting the whole equipment, including inspections one by one on each part of the bench and each of the sub-systems. Such inspections waste more time and cost. As far as the existing techniques are concerned, there is no provision of a system or method capable of rapid and effective inspections and fit for use in a memory repair analysis apparatus for all kinds of memory test equipments produced by the enterprises.
Therefore, it is desirable to provide an improved semiconductor test system for inspecting a memory IC chip and with self-inspection of a memory repair analysis device to mitigate and/or obviate the aforementioned problems.